Description
XiangShan (open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) has improper gating of its distributed CSR write-enable path, allowing illegal CSR write attempts to alter custom PMA (Physical Memory Attribute) CSR state. Though the RISC-V privileged specification requires an illegal-instruction exception for non-existent/illegal CSR accesses, affected XiangShan versions may still propagate such writes to replicated PMA configuration state. Local attackers able to execute code on the core (privilege context depends on system integration) can exploit this to tamper with memory-attribute enforcement, potentially leading to privilege escalation, information disclosure, or denial of service depending on how PMA enforces platform security and isolation boundaries.
INFO
Published Date :
2026-04-21T00:00:00.000Z
Last Modified :
2026-04-21T17:59:06.506Z
Source :
mitre
AFFECTED PRODUCTS
The following products are affected by CVE-2026-29644 vulnerability.
| Vendors | Products |
|---|---|
| Openxiangshan |
|
REFERENCES
Here, you will find a curated list of external links that provide in-depth information to CVE-2026-29644.
