Description

Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.

INFO

Published Date :

2025-07-01T00:00:00.000Z

Last Modified :

2025-07-02T13:58:38.672Z

Source :

mitre
AFFECTED PRODUCTS

The following products are affected by CVE-2025-45006 vulnerability.

No data.

REFERENCES

Here, you will find a curated list of external links that provide in-depth information to CVE-2025-45006.

URL Resource
https://github.com/chipsalliance/rocket-chip.git cve-icon cve-icon
https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.md cve-icon cve-icon
https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications cve-icon cve-icon
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CVSS Vulnerability Scoring System

Detailed values of each vector for above chart.
Attack Vector
Attack Complexity
Privileges Required
User Interaction
Scope
Confidentiality Impact
Integrity Impact
Availability Impact