Description

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

INFO

Published Date :

2026-01-14T10:58:44.342Z

Last Modified :

2026-01-20T15:21:14.551Z

Source :

Arm
AFFECTED PRODUCTS

The following products are affected by CVE-2025-0647 vulnerability.

Vendors Products
Arm
  • C1-premium
  • C1-premium Firmware
  • C1-ultra
  • C1-ultra Firmware
  • Cortex-a710
  • Cortex-a710 Firmware
  • Cortex-x2
  • Cortex-x2 Firmware
  • Cortex-x3
  • Cortex-x3 Firmware
  • Cortex-x4
  • Cortex-x4 Firmware
  • Cortex-x925
  • Cortex-x925 Firmware
  • Neoverse-n2
  • Neoverse-n2 Firmware
  • Neoverse-v2
  • Neoverse-v2 Firmware
  • Neoverse-v3
  • Neoverse-v3 Firmware
  • Neoverse-v3ae
  • Neoverse-v3ae Firmware
  • Neoverse N2
REFERENCES

Here, you will find a curated list of external links that provide in-depth information to CVE-2025-0647.

URL Resource
https://developer.arm.com/documentation/111546 cve-icon cve-icon
https://graph.volerion.com/view?ID=CVE-2025-0647 cve-icon cve-icon
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